On-delay circuit

ABSTRACT

The present invention relates to a fail-safe on-delay circuit which uses an an electronic circuit. An input signal higher than a power source potential is input to a PUT oscillating circuit and a pulse signal generated with a predetermined time constant, is once changed in a level conversion circuit to a level within a range of the power source potential, and then is phase inverted and a rising differential signal of the phase inverted signal is formed. The input signal to the PUT oscillation circuit is applied to one input terminal of a fail-safe two input window comparator, and the differential signal is input to the other input terminal, and self held. After a predetermined delay time an output of logic value 1 is generated from the window comparator. As a result a fail-safe on-delay circuit can be made wherein, in the event of a fault in the elements of the circuit the delay time is not shortened.

TECHNICAL FIELD

The present invention relates to a fail-safe on-delay circuit which usesan electronic circuit, and wherein a pre-set delay time is not shortenedin the event of a fault.

BACKGROUND ART

Heretofore, fail-safe on-delay circuits using a resistor and fourterminal capacitor, as disclosed for example in U.S. Pat. No. 4,667,184by Futsuhara, have been used for contactless type on-delay circuitsemploying conventional electronic circuits.

As shown in FIG. 1, such an on-delay circuit 1, comprises a resistor R1,a four terminal capacitor C1, and a two input window comparator WC whichgenerates an output of logic value 1 when a signal of a level higherthan a power source voltage is input to both input terminals A and B.

With this circuit, the input resistance of the window comparator is madesufficiently high compared to that of the resistor R1, so that when aninput signal of y=1 (an input signal of a level higher than the powersource potential Vcc) is input to a signal input terminal Uy of theon-delay circuit 1, the four terminal capacitor C1 is charged, and thecharged voltage is applied to both input terminals A and B of the windowcomparator WC. When the signal level of the input to the input terminalsA and B exceeds a threshold value pre-set for the window comparator WCand which is higher than the power source potential Vcc, the windowcomparator WC generates an output, and an output signal z=1 of logicvalue 1 is generated as the output of the on-delay circuit 1.Accordingly, with the on-delay circuit 1, the oscillation delay, that isthe delay time of the on-delay circuit 1, is determined by the resistorR1, the four terminal capacitor C1 and the threshold value of the windowcomparator WC.

Another type of on-delay circuit using a UJT (uni-junction transistor)is proposed by Futsuhara in Japanese Examined Patent Publication No.1-3006, and in The Transaction of The Institute of Electrical Engineersof Japan Vol. 104-C, No.2 (February 1984) PP. 1˜6.

With these on-delay circuits, the former on-delay circuit has afail-safe construction, since in the event of a disconnection fault inthe resistor, or a disconnection or short circuit fault in the terminalsof the four terminal capacitor, an output is not generated. However, thetime delay cannot be set very long. If a long time delay is required,then there is no other way but to use mechanical type timers such as amotor timer wherein the rotation of a motor is reduced in speed througha speed reducer to operate contact points.

With the latter on-delay circuit using a UJT, this has disadvantagessuch as; (1) erroneous signal generation due to a short circuit faultbetween the terminals of the UJT itself is not covered, and (2) sincethere is no threshold value operation function provided in the circuitwhich stores the delay pulse signal, the abovementioned erroneous signalgeneration cannot be dealt with.

The present invention takes into consideration the abovementionedsituation with the object of providing a practical on-delay circuitusing a fail-safe electronic circuit, which covers all possible failuremodes.

DISCLOSURE OF THE INVENTION

The on-delay circuit of the present invention comprises; a PUToscillation circuit for conducting a PUT (programmable uni-junctiontransistor) with a predetermined delay time from applying a signal to asignal input terminal, to generate an oscillating pulse, a levelconversion circuit for level converting the signal level of theoscillating pulse from the PUT oscillation circuit, a two input windowcomparator for generating an output of logic value 1 when a signal inputby way of the signal input terminal of the PUT oscillation circuit isapplied to a first input terminal, a rising differential signal of theoutput from the level conversion circuit is applied to a second inputterminal, and signals of a level higher than a power source potentialare input to the first and second input terminals, and a self holdingcircuit which feeds back a rectified output of the two input windowcomparator to the second input terminal side, to thereby self hold theoutput of the window comparator.

With the on-delay circuit of such construction, the oscillating pulse isgenerated from the PUT with a delay time determined by the resistancevalue of first through third resistors, and the capacity of a capacitor.This pulse is phase inverted in the level conversion circuit and changedto a level within the frame of the power source, after which the risingdifferential signal is input to the second input terminal of the windowcomparator, so that an output is generated from the window comparator.

By this method of once converting the level of the oscillating pulse ofthe PUT oscillation circuit in the level converting circuit, andinputting the rising differential signal to the window comparator, thenan output of logic value 1 will not be generated from the windowcomparator not only for a disconnection fault in the respective of theresistors, or for a disconnection or short circuit fault in thecapacitor, but also with a short circuit fault between the terminals ofthe PUT. Also when the window comparator is faulty, an output of logicvalue 1 will not be generated. Hence a fail safe construction becomespossible.

Moreover, if a circuit for setting a time constant, comprising aresistor and four terminal capacitor, is provided prior to the firstinput terminal of the two input window comparator which takes the signalinput by way of the signal input terminal of the PUT oscillationcircuit, then even in the event of a multiple fault wherein severalcircuit components such as the resistors and capacitor(s) failsimultaneously, it is possible to maintain the fail-safecharacteristics.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram illustrating an example of a conventionalon-delay circuit;

FIG. 2 is a circuit diagram illustrating a first embodiment of anon-delay circuit according to the present invention;

FIG. 3 is a diagram for explaining an operation of the on-delay circuitof FIG. 2;

FIG. 4 is a diagram for explaining the fail-safe characteristics of thecircuit of FIG. 2;

FIG. 5 is a diagram illustrating an example of a supposed failure modefor the on-delay circuit of FIG. 2;

FIG. 6 is a circuit diagram for dealing with the failure mode of FIG. 5;

FIG. 7 is a diagram for illustrating an operation of the circuit of FIG.6;

FIG. 8 is a diagram for explaining the principle of fail-safe signalprocessing;

FIG. 9 is an example of a circuit for a fail-safe amplifier;

FIG. 10 is an example of a different circuit for a fail-safe amplifier;

FIG. 11 is a circuit diagram for a case where an output signal of analternating current amplifier is rectified by a transformer junction;

FIG. 12 is a circuit diagram of a two input window comparator applicableto the present invention; and

FIG. 13 is a characteristic curve for the window comparator of FIG. 12.

BEST MODE FOR CARRYING OUT THE INVENTION

As follows is a detailed description of embodiments of the presentinvention with reference to the drawings.

FIG. 2 shows an example of a practical fail-safe on-delay circuit usinga CR circuit, illustrating a first embodiment of an on-delay circuitaccording to the present invention.

As shown in FIG. 2, an on-delay circuit 10 of the present inventioncomprises; a known PUT oscillation circuit 11 which conducts a PUT(programmable-uni-junction transistor) to generate an oscillating pulsewith a predetermined delay time from applying a signal to a signal inputterminal Uy, a level conversion circuit 12 for converting the outputsignal from the PUT oscillation circuit 11 so as to change below thepower source potential Vcc, and inverting its phase, a two input windowcomparator (referred to hereunder as a window comparator) WC similar tothe device of FIG. 1, which generates an output of logic value 1 whensignals of a level higher than a power source potential are inputtogether to a first input terminal A and a second input terminal B, anda self holding circuit comprising a rectifying circuit 13 for rectifyingan output of the window comparator WC and a feedback resistor Rf whichfeeds back an output signal of the rectifying circuit 13 to the secondinput terminal B side.

The PUT oscillation circuit 11 has a series circuit of a first resistorR₀₁ and a capacitor C₀₁ connected between the signal input terminal Uyand a power supply line L to the window comparator, and has a seriescircuit of a second resistor R₀₂ and a third resistor R₀₃ connected inparallel with the series circuit of the first resistor R₀₁ and thecapacitor C₀₁. The PUT anode terminal A is connected to an intermediatepoint between the first resistor R₀₁ and the capacitor C₀₁, and the PUTgate terminal G is connected to an intermediate point between the secondresistor R₀₂ and the third resistor R₀₃. The PUT cathode terminal K isconnected through a fourth resistor R₀₄ to the power supply line L, andan oscillating pulse is generated from an intermediate point between thePUT cathode terminal K and the fourth resistor R₀₄.

The level conversion circuit 12 has a fifth resistor R₀₅ and a sixthresistor R₀₆ for voltage dividing the oscillating pulse signal voltagefrom the PUT oscillation circuit 11, and incorporates a PNP transistorQ₀ with the emitter connected to the power supply line L of the windowcomparator WC, the collector connected through a seventh resistor R₀₇ toearth, and the base connected to an intermediate point between the fifthresistor R₀₅ and the sixth resistor R₀₆. An output is generated from anintermediate point between the collector of the transistor Q₀ and theseventh resistor R₀₇. A capacitor C₀₂ and a diode D₀₁ are used forproducing a rising differential signal from the level conversion circuit12 output signal, and inputting this into the second input terminal B ofthe window comparator WC.

The two input window comparator WC comprises a plurality of resistorsand transistors, and is constructed so as to generate an output of logicvalue 1 corresponding to a high energy condition, only when signals of apredetermined level higher than the power source potential are inputsimultaneously to the two input terminals A and B. Moreover, it has afail-safe construction, with the output becoming a logic value of "0"corresponding to a low energy condition, in the event of a fault. Such afail-safe two input window comparator will be explained in detail later.

The operation of the on-delay circuit 10 will now be described using thetime chart of FIG. 3.

When the input signal y=1 (input signal of a level higher than the powersource potential Vcc that is, input signal of level V shown in FIG. 3)is supplied to the terminal Uy, this signal is input to the first inputterminal A of the window comparator WC. As well as this, after a delaytime τ provided to the input voltage V, determined by the time constantfixed by the resistance value of the first resistor R₀₁ and the capacityof the capacitor C₀₁, and by the divided voltage ratio for the secondresistor R₀₂ and the third resistor R₀₃, the PUT conducts and anoscillating output P₁ is generated (the window of the first inputterminal A of the window comparator WC is set so that the input level Vis greater than the lower limit threshold value ThAL). This oscillatingoutput P₁ is phase inverted by the transistor Q₀ to become an outputsignal P2, and the rising signal of the output signal P₂ is input to thesecond input terminal B of the window comparator WC by way of thecapacitor C₀₂ as a differential signal P3. When the signal P₃ is inputto the window comparator WC, the window comparator WC oscillates, andthe oscillating output signal is rectified by the rectifying circuit 13and fed back to the input terminal B by way of a feedback resistor Rf.As a result, even if the differential signal P₃ of the signal P₂ islost, the window comparator WC continues to oscillate until the inputsignal "y" becomes lower than the lower threshold value ThAL of thefirst input terminal A, while self holding the signal P₃.

The fail-safe construction of the on-delay circuit 10 of FIG. 2 will nowbe described.

In this respect, it is supposed that the resistors are susceptible tomechanical or heat failure, while the plates of the electrodes making upthe capacitor are made from a non volatile material. There willtherefore be a small change in temperature of the resistance value andthe electrostatic capacity. However from the fail-safe point of view itis sufficient to consider the resistors with respect to disconnectionfaults only, and to consider the capacitors with respect to leaddisconnection faults and short circuit faults between the electrodeplates. Further, it is supposed that PUT oscillation circuit 11 and thelevel conversion circuit 12 are not such that there is occurrence ofself oscillation in spite of there being no input signal. Then, the PUToscillation circuit 11 will only oscillate and generate an output pulseP₁, when the elements constituting the circuit are in a normalcondition, and the input signal "y" reaches a level exceeding the lowerlimit threshold value ThAL of the first input terminal A of the windowcomparator WC (for ease of understanding the threshold value of theupper limit is set sufficiently higher than the input signal level,however, even though set in this way, the function as a fail-safeon-delay circuit is not lost).

Moreover, even if for example a disconnection fault occurs in the first,second and third resistors R₀₁, R₀₂, R₀₃, or the beforementioneddisconnection or short circuit fault occurs in the capacitor C₀₁, or adisconnection fault occurs in the three electrodes A (anode), K(cathode), and G (gate) of the PUT or a short circuit occurs between theelectrodes, the output signal P₁ is not generated. However, since thefourth resistor R₀₄ together with the capacitor C₀₁ determines the pulsewidth τ' of the output signal P1, and a disconnection fault occurs inthe fourth resistor R₀₄, then the pulse width τ' of the signal P1 isincreased. Hence, the delay period (τ+τ') of the on-delay circuit 10becomes a little longer. However, since an increase in delay time is onthe safe side, then this presents little problem.

The purpose of the level conversion circuit 12 is to change the pulsesignal P₁ generated with a pulse level higher than power sourcepotential Vcc, within the frame of the power source potential Vcc asshown by P₂ in FIG. 3. If the on-delay circuit is constructed with theoscillating output signal P₁ of the PUT led directly to the second inputterminal B of the window comparator WC by way of the diode D₀₂ asindicated by the chain line of FIG. 2, then the level conversion circuit12 can be omitted. However, if a disconnection fault occurs in the thirdresistor R₀₃, and furthermore a short circuit fault occurs between thegate G and the cathode K, then when the input signal "y" is input, thesignal "y" is input directly to the first and second input terminals Aand B of the window comparator WC. As a result, during the time that thedelay period τ is not being produced, the window comparator WCoscillates, resulting in a dangerous situation. To prevent this danger,the signal P₁ is once converted to the signal P₂ which is within theframe of power source potential Vcc. This signal P₂ is then overlappedwith the power source potential Vcc using the capacitor C₀₂ and thediode D₀₁ and input to the second input terminal B of the windowcomparator WC.

The level conversion circuit 12 has one more important function. Therising signal of signal P₂ as shown by P₃ in FIG. 3 is input to thesecond input terminal B of the window comparator WC. It means that therising signal P₃ can generate an output pulse successively after the PUToscillation circuit 11 oscillates and outputs the output signal P₁. Inother words, this rising signal P₃, provides proof that the PUToscillation circuit 11 is operating normally. Even in a worst casescenario where a disconnection fault occurs in the third resistor R₀₃and the input signal "y" is supplied directly to the base of thetransistor Q₀ by way of the second resistor R₀₂, and between the gateterminal G and the cathode terminal K of the PUT, then since the risingsignal of the input signal "y" becomes the falling signal in the outputsignal P₂ of the transistor Q₀, then it does not become the signal P₃transmitted by the capacitor C₀₂ and the diode D₀₁.

In the on-delay circuit 10 of FIG. 2, the first input terminal A of thewindow comparator WC compensates for the weakness of the PUT oscillationcircuit 11. In this regard, the delay operation of the PUT oscillationcircuit 11 will be described with reference to the time chart of FIG. 4.

In FIG. 4, symbol Vc₀₁ indicates the change in the terminal voltage ofthe capacitor C₀₁ on the first resistor R₀₁ side. The setting of thecircuit is such that the input signal "y" rises to voltage V whilecharging the capacitor C₀₁ through the first resistor R₀₁, and thenafter τ seconds, the output signal P₁ is generated. However if in aworst case situation, the level V of the input signal "y" drops to V'before the τ seconds has elapsed, and the potential of the gate terminalG of the PUT drops accordingly with the change in input level, then anoutput pulse P₁ ' occurs at the point in time of τ1, prior to the τseconds. Here if the lower limit threshold value ThAL of the first inputterminal A of the window comparator WC is set so that the input level V'becomes lower than the lower limit threshold value ThAL of the firstinput terminal A, then even in the worst case where there is a levelchange in the input signal "y" from V to V', and the pulse P₁ ' is inputto the second input terminal B at the point in time of τ1, prior to thepredetermined time τ, the window comparator WC will not oscillate.

Hence, the threshold value ThAL of the first input terminal A,determines the minimum value of the delay time τ. Needless to say a UJT(uni-junction transistor, also referred to as a double base diode) canbe used instead of a PUT.

In the construction of the on-delay circuit 10 of FIG. 2, an inputsignal "y" greater than the power source potential Vcc is input, and anoscillation pulse P₁ which is output at a potential higher than thepower source potential Vcc is once converted into a pulse P₂ whichchanges within the frame of the power source potential Vcc. This pulseP₂ is then converted to a pulse P₃ having a potential higher than thepower source potential Vcc, to become an input signal to the secondinput terminal B of the window comparator WC. Due to this conversion,the construction is such that only when a pulse P₂ arises in the levelconversion circuit 12 is the pulse P₃ input as a trigger signal to thesecond input terminal B of the window comparator WC.

However, when a disconnection fault occurs for example in the fourthresistor R₀₄, the sixth resistor R₀₆, and the seventh resistor R₀₇, andthe capacitor C₀₁, and a disconnection fault occurs in the collector ofthe transistor Q₀, then the on-delay circuit 10 of FIG. 2 essentiallybecomes that of FIG. 5. In practice, such a multiple failure is notlikely to occur at the same time. However in the case where, due to afault in the components of the circuit, a signal higher than the powersource potential Vcc is erroneously input to the second input terminal Bof the window comparator WC, then at this time the circuit becomes thatof FIG. 5. To positively ensure that under these highly unfavourableconditions an incorrect output signal of z=1 is not produced, then asshown in FIG. 6 a delay circuit similar to that of FIG. 1 comprising aresistor R₂₂₁ and a four terminal capacitor C₂₂₁, is inserted in theon-delay circuit 10 of FIG. 2 prior to the first input terminal A of thewindow comparator WC. Moreover, the upper and lower limit thresholdvalues ThBH and ThBL can be set a fault in the second input terminal Bin consideration of faults.

With such a circuit, then in a worst case situation as illustrated byFIG. 5, the case indicated by (1) for where the capacitor C₀₂ isoperating normally, can be distinguished from the case indicated by (2)for the short circuit fault in the capacitor C₀₂.

Case (1) as shown in the time chart of FIG. 7 by the waveform (1) of P₃,is for when the rising signal (differential signal) of the input signal"y" is input passing between the anode terminal A and the cathodeterminal K, or between the gate terminal G and the cathode terminal K ofthe PUT. If this differential signal P₃ attains a level that satisfiesthe oscillation conditions at the second input terminal B of the windowcomparator WC, then in the case where due to the abovementioned multiplefailure the circuit construction becomes that of FIG. 5, the windowcomparator WC produces an output signal of z=1 simultaneously with inputof the input signal "y" (a delay time of τ does not occur). The resistorR₂₂₁ and the four terminal capacitor C₂₂₁ of FIG. 6 are inserted toavoid this. The resistor R₂₂₁ and the four terminal capacitor C₂₂₁ havethe same function as for the case of the resistor R₁ and the fourterminal capacitor C₁ in FIG. 1.

In this respect, the signal (shown as y_(A) in FIG. 6) for input to thefirst input terminal A of the window comparator WC, as shown in FIG. 7reaches the lower limit threshold value ThAL, τ2 seconds (τ2 is a timeconstant determined by the resistor R₂₂₁ and the four terminal capacitorC₂₂₁) after input of the input signal y=1 (signal for level V). Here ifthe lower limit threshold value ThBL of the second input terminal B ofthe window comparator WC is set so that the time τ3 taken from the riseof the signal P₃ until it becomes less than the lower limit thresholdvalue ThBL set for the second input terminal B of the window comparatorWC, becomes shorter than the above time constant τ2, then even if thesignal P₃ is generated due to the rising of the input signal y=1, anoutput signal of z=1 does not occur.

The situation of case (2) wherein a short circuit fault occurs in thecapacitor C₀₂ will now be described.

Here the input resistance of the second input terminal B of the windowcomparator WC is made r_(in), the resistance values of the resistorsR₀₁, R₀₂, R₀₃, R₀₄, R₀₅ are made r₀₁, r₀₂, r₀₃, r₀₄, r₀₅, and undernormal conditions r₀₁ >>rin>>r₀₂, r₀₃, r₀₄ >>r₀₅. In an extremecondition where a short circuit fault occurs between the anode terminalA and cathode terminal K of the PUT, then since r₀₁ >>rin, the inputvoltage to the second input terminal B drops, so that the lower limitthreshold value ThBL can become higher than this input voltage.Subsequently, when as another different extreme condition, a shortcircuit fault occurs between the gate terminal G and the cathodeterminal K of the PUT, the signal comprised of the input voltage V whichis voltage divided by the resistors R₀₂ and R₀₃, is input to the secondinput terminal B.

Since generally, this voltage divided ratio (resistance value ratio r₀₂/r₀₃) is approximately 0.7, then this is shown as 0.7 V in the timechart of FIG. 7. Consequently, the upper limit threshold value ThBH ofthe second input terminal B of the window comparator WC may be set to avalue which is lower than this input voltage (for example 0.5 V). If adisconnection fault occurs in the resistor R₀₃ shown in FIG. 5, then aninput voltage larger than the beforementioned 0.7 V is input to thesecond input terminal B of the window comparator WC. Moreover, when ashort circuit fault occurs simultaneously between the anode terminal Aand the cathode terminal K, and the gate terminal G and the cathodeterminal K of the PUT, then since r₀₁ >>r₀₂, this short circuit faultcondition is approximately equivalent to the short circuit conditionsbetween the gate terminal G and the cathode terminal K. Furthermore,under conditions wherein there is no disconnection fault in the resistorR₀₄, then since r₀₄ <<r₀₂ and ro₀₁, the input voltage of the secondinput terminal B of the window comparator WC is at a low level.

With the on-delay circuit shown in FIG. 6 comprising the resistor R₂₂₁and four terminal capacitor C₂₂₁ attached to the on-delay circuit 10 ofFIG. 2, then under normal conditions with no faults, a signal (shown asP₃ ' in FIG. 7) is produced at the second input terminal B of the windowcomparator WC after τ seconds from input of signal "y". Even if theheight of this pulse signal P₃ ' exceeds the threshold value ThBH of thesecond input terminal B, this does not cause any problems. This isbecause if, prior to generation of the signal P₃ ', the input signalY_(A) of the first input terminal A exceeds the lower limit thresholdvalue ThAL, then the rise of the signal P₃ ' generated after τ seconds(dP₃ '/dt)>0) or the fall thereof (dP₃ '/dt<0) comes between the rangeof the window given by the threshold values ThBH and ThBL, so thatwindow comparator WC oscillates, enabling the signal to be self held(with an error of Δτ).

Thus with an on-delay circuit wherein a delay circuit comprising theresistor R₂₂₁ and the four terminal capacitor C₂₂₁ of FIG. 1 is fittedin this way prior to the second input terminal A of the windowcomparator WC of the on-delay circuit 10 of FIG. 2, and upper and lowerlimit threshold values ThBH and ThBL for an error signal produced by afault in the circuit and having a potential higher than the power sourcepotential Vcc, are determined for the second input terminal B of thewindow comparator WC, then an on-delay circuit can be provided which canbetter prevent erring to the danger side due to circuit faults (errorsshortening the delay time).

With the present invention, the input signal to the on-delay circuitmust be at a direct current potential higher than the power sourcepotential Vcc which drives the circuit. Such an input signal, that is,one of potential higher than the power source potential Vcc may be inputsimply by means of a switch. Another situation however involving inputof an input signal of a potential higher than the power source potentialVcc is that wherein such potential is produced as a result of fail-safesignal processing. A fail-safe signal processing method has beenpreviously described for example in relation to a magnetic sensor in apaper by M. Karo, K. Futsuhara, M. Mukaidono in the Proc. of 2ndInternational Conf. on Human Aspects of Advanced Manufacturing andHybrid Automation, Honolulu, U.S.A. (August 1990), entitled"Construction of Magnetic Sensors for Assuring Safety". The theoryforming the basis of fail-safe signal processing however is notdescribed in detail. A method of fail-safe signal processing willtherefore now be described using an example of a light beam sensorillustrated by FIG. 8.

In the construction of FIG. 8, a light beam B is projected from aprojector T to a danger region W (region where safety is to beverified), and this light signal (alternating current) is received by alight receiver R. The light receiver R comprises a light receivingelement, an amplifier for amplifying the output signal therefrom, and arectifying circuit for rectifying the output signal from the amplifier.

The sensor of FIG. 8 carries out the following three important steps(1˜3) discussed below, as a fail-safe steps.

(1) The input signal to the light receiver R is made an alternatingcurrent signal.

As shown by the oscillation between B1 and B0 in FIG. 8, the outputsignal of the projector T (light beam B) is transmitted to lightreceiver R, as an alternating signal, wherein a fight present condition(B1) and a light absent condition (B0) are output alternately. With thismethod, from the point of view of the light receiver R side, a level ofB1 (light present) implies that the light beam is not cut off by anobstacle (i.e. a safe condition) while a level of B0 (light absent)implies that the light beam is cut off by an obstacle (i.e. an unsafecondition). The light receiving element and the amplifier whichconstitute the light receiver R take this alternating signal and amplifyit. Thus when an obstacle is actually in the region W, the alternatingsignal is not received, while when the obstacle is absent, thealternating signal is received. In other words with this method, evenwhen there is no obstacle (i.e. a safe condition), the received signalindicating this also includes the signal (B0) indicating danger.

(2) The signal y=1 indicating safety is made a rectified output signalof the alternating current signal.

The output signal of the amplifier in FIG. 8 is rectified by a voltagedoubler rectifying circuit to give a direct current output signal y=0.In FIG. 8, only after the input signal level B0 (indicating danger) isreceived by capacitor CA, a charge of the polarity shown in FIG. 8 takesplace through a diode DA. Then the input signal level B1 (indicatingsafety) superimposes on this charging voltage and is stored in thecapacitor CB through a diode DB as a direct current output voltage VDC.This stored voltage VDC is not produced as long as the capacitor CA isnot being charged with the input signal level B0. That is, the directcurrent output voltage VDC indicating safety is only produced when theinput signal level B0 indicating danger is received.

The receiving method illustrated by FIG, 8, can verify when generatingthe signal indicating safety (VDC), that the light receiving element andthe amplifier are able to indicate danger. If this operation isexpressed logically, then an output signal y=1 is produced by thelogical product of; the region W is safe: and the light receiver R isable to indicate danger. If the input signal level B1 is not received,the direct current output voltage VDC is not produced, thus indicatingdanger. Therefore in FIG. 8, the alternating light beam B sent from theprojector T checks whether or not there is an obstacle in the dangerregion W, and at the same time acts as a check signal for checkingwhether or not the light receiving element and the amplifier of thelight receiver R are operating normally.

(3) The output signal is output at a level higher than the power sourcepotential.

In FIG. 8, the voltage doubler rectifying circuit is clamped at thepower source potential Vcc using the diode DA, and the signal "y" isoutput with the rectified output voltage VDC superimposed with the powersource potential Vcc. The reason for generating an output signalsuperimposed in this way with the power source potential (referred to asan output signal of potential outside the power source frame) is that,even in an extreme case as shown by the dotted line in the FIG. 8wherein a short circuit fault occurs in the capacitor CA so that thepower source potential Vcc is output directly to the output side, thenthis can be distinguished at the output side, from the output potentialVDC. That is to say, if in FIG. 8 the output potential of the voltagedoubler rectifying circuit is V, then the binary output signal "y" isdetermined as follows; ##EQU1##

Thus, when an output potential higher than the power source potentialVcc (V>Vcc) is output this gives a signal y=1 indicating safety, whilewhen an output potential equal to or lower than the power sourcepotential Vcc (V≦Vcc) is output, this gives a signal y=0 indicatingdanger.

By giving the signal y binary in this way, then even in an extreme casewherein a short circuit fault occurs in the capacitor CA, and the powersource potential Vcc is output to the output side, there is no erroneousgeneration of a signal y=1 indicating safety.

With the above example, the rectified output signal must be level testedusing a threshold value of a level higher than the power sourcepotential. Moreover, the circuit used for this level test must have thecharacteristics that; "there is never an occurrence of a level testoutput wherein, in spite of the input level being below the thresholdvalue, due to a fault the output erroneously becomes as though a levelhigher than the threshold value has been input". A level test circuithaving such functions is the fail safer window comparator to bedescribed later.

The alternating current amplifier in FIG. 8 also must have fail-safecharacteristics. Such an amplifier will now be described.

The normal transistor amplification level, is reduced due to a fault,but never increase more than 30%. At the time of a fault, the outputsignal is thus fixed to a certain level unless the transistor amplifierwill not self oscillate. Because of this, with the fail-safe amplifierusing an alternating current signal for the input signal, output of thealternating current signal as an output signal having a predeterminedamplitude constitutes normal operation of the amplifier. This isbecause, in an extreme case, where a fault occurs in the amplifier, theoutput level becomes fixed at a certain value (level) does not become analternating current output signal. The basic condition of this thinkingis that the amplifier does not self oscillate. Consequently, a negativefeedback amplifier is not really suitable as a fail-safe amplifier. Anegative feedback amplifier however has the advantage that theamplifying level is hardly changed with temperature. The thinking isbased on that the input signal level is small, and accordingly, due to afault in the amplifier, the input signal is output directly to theoutput side without amplification, "since the output level is small, theoutput signal will not exceed the threshold value prepared for theoutput side."

FIG. 9 shows an example of a fail-safe negative feedback amplifier(capable of amplifying to approximate 30 dB )

In FIG. 9, symbols R191, R192, R193, R194, R195, R196 indicateresistors, C191, C192, C193 indicate capacitors, while Q191, Q192indicate transistors. The output signal is feedback from the emitterside of the transistor Q192 through the resistor R196 to the base of thetransistor Q191. In the circuit of FIG. 9, if at first a disconnectionfault occurs in the resistors R191, R192, R193, R194, R196, the outputsignal of the transistor Q192 becomes fixed at either a high or lowoutput level. Similar output conditions also result when a short circuitfault occurs in the capacitor C192, since this will change the base biasof the transistor Q191 considerably. When a disconnection fault occursin the capacitor C192 and a disconnection fault occurs in the resistorR195, the amplification level drops and the amplitude of the output fromthe transistor Q192 is reduced. However, when such a fault occurs, forfixing the output signal of the transistor Q192 at a constant level.,then the construction can be that of FIG. 10.

In FIG. 10, with the exception of the resistors R194', R195', and thecapacitor C192', the other elements are the same as those of FIG. 9.

In FIG. 9, the emitter resistance of the transistor Q192 with respect tothe alternating current signal is the combined resistance of resistorsR194 and R195 in parallel. The resistance of resistor R195' in FIG. 10may be made approximately equal in size to this resistance. In FIG. 9,the emitter resistance of transistor Q192 with respect to a directcurrent signal is the resistance of resistor R194. In FIG. 10 the totalresistance of resistors R195' and R194' may be made approximately equalto this size. In FIG. 10, a four terminal capacitor is used as thecapacitor C192', so that even if a disconnection fault occurs in one ofthe resistors R194', R195', and even if a short circuit or adisconnection fault occurs in the capacitor C192', the output signal ofthe transistor Q192 is fixed at the specific direct current level.

Moreover, in FIG. 8, the output signal of the rectifier is generated bycapacitor coupling. It is well known however that the output signal ofthe amplifier can be generated using transformer coupling as shown bythe circuit of FIG. 11, and rectifying the secondary side output signalin a rectifying circuit.

In the circuit of FIG. 11, the role of the coupling capacitor in FIG. 8is carried by the transformer T. The secondary side output signal fromthe transformer T can be considered to prove by the average value levelOav of the amplitude of the alternating current output signal, as shownin FIG. 11 that a period when there is no alternating current inputsignal, that is to say the proof that a danger condition can be shown asthe output signal of the transformer T. Passing through Oav1, . . . Oavnby the output signal of transformer T equals to that the field of thetransformer T has changed. This proves that the input signal of thetransformer T has changed to the side indicating danger.

The construction of the beforementioned two input window comparator usedin the present invention, will now be described in detail.

The fail-safe window comparator circuit, its operation and fail-safecharacteristics are disclosed in Trans. IEE of Japan Vol. 109-C, No. 9September 1989 under the heading "A Construction Method for an InterlockSystem using a Fail-Safe Logic Element having Window Characteristics".Moreover this is also disclosed in literature such as the Proc. of 19thInternational Symp. on Multiple-Valued Logic, IEEE Computer Society (May1989) under the heading of "Application of Window Comparator to MajorityOperation", and the IEEE TRANSACTION on INSTRUMENTATION AND MEASUREMENT,Vol. 38, No. 2(April, 1989) under the heading of "Realization ofFail-Safe Train Wheel Sensor Using Electromagnetic Induction".Furthermore, a two input fail-safe window comparator incorporated in anLSI is disclosed in IEICE TRANS. ELECTRON., Vol, E76-C, No. 3, March1993 PP. 419-427 under the heading of "LSI Implementation and SafetyVerification of Window Comparator Used in Fail-Safe Multiple-ValuedLogic Operation". The fail-safe window comparator circuit has also beenpreviously disclosed by one of the present inventors in U.S. Pat. Nos.4,661,880, 5,027,114 and in Japanese Examined Patent Publication No.1-23006.

A representative circuit example and details of its operation will nowbe given.

FIG. 12 is a circuit diagram of a fail-safe window comparator. Since thecircuit of FIG. 12 has a fail-safe logical product function this is atwo input fail-safe window comparator/AND gate, to be precise.

In FIG. 12, symbols R10, R20 through R170, R180 indicate resistors, Q1through Q7 indicate transistors, A, B indicate input terminals, Vccindicates the power source potential for the window comparator, andnumeral 203 indicates a rectifying circuit. The areas in FIG. 12outlined by chain lines comprise direct-coupled direct currentamplifying circuits 201, 202 which use respective transistors Q1, Q2,Q3, and Q5, Q6, Q7. Both have identical direct current amplifyingcircuit constructions. The circuits differ from a general direct currentamplifying circuit in that the transistor Q1 and the transistor Q5operates at a potential higher than the power source potential Vcc (theemitters of the NPN transistors Q1 and Q5 are connected to the powersource potential Vcc). Consequently, an input signal having a voltagehigher than the power source potential Vcc must be supplied to the basesof the transistors Q1 and Q5. The collectors of the transistors Q1 andQ5 are connected to the input terminals A, B through respectiveresistors R10 and R110. It will be apparent that as long as inputsignals higher than the power source potential Vcc (referred to as aninput signal of potential outside the frame of the power source) are notsupplied to the input terminals A, B, then the transistor Q1 and thetransistor Q5 will not operate as amplifiers. Transistor Q4 constitutesa phase inversion circuit (inverter) and has an inverting amplificationfunction on the output signal from the direct current amplifying circuit201. Transistor Q4 also, as with transistors Q1 and Q5, operates with abase input potential and collector input potential (supplied from theinput terminal A via resistor R90) higher than the power sourcepotential Vcc. The base input signal to the transistor Q5 is suppliedfrom the collector of the transistor Q4. Therefore if a signal of ahigher input level than the power source potential Vcc is applied to theinput terminal A, then a signal of a potential higher than the powersource potential Vcc is supplied to the base of the transistor Q5.

The emitters of both transistors Q3 and Q7 are at earth potential, whilethe collectors are connected to the input terminals A and B by way ofrespective resistors R60, R70, and R160, R170. Consequently, if an inputsignal of a potential higher than the power source potential Vcc isapplied to the input terminals A and B, then the collector potentials ofthe transistor Q3 and the transistor Q7 become earth potential when thetransistors respectively come ON, and become the potential of the inputterminals, that is potential higher than the power source potential Vcc,when the transistors respectively go OFF. Since the switch signalresulting from switching the transistor Q3 and the transistor Q7 on andoff is respectively supplied to the base of the transistor Q4 by way ofthe resistor R80, and to the base of the transistor Q1 by way of theresistor R180, the transistor Q4 and the transistor Q1 can berespectively switched on and off using the output signal of thecollector of the transistor Q3 and the output signal of the collector ofthe transistor Q7.

That is to say, the circuit of FIG. 12 constitutes a feedbackoscillator, with the direct current amplifying circuit 201direct-coupled to the direct current amplifying circuit 202 by way ofthe transistor Q4, and the output signal of the direct currentamplifying circuit 202 direct-coupled to the direct current amplifyingcircuit 201 by way of the resistor R180.

Conditions for oscillation of the circuit of FIG. 12 are determined bythe following equations, where V10 is the input potential of the inputterminal A, and V20 is the input potential of the input terminal B;

For the input terminal A

    (r.sub.10 +r.sub.20 +r.sub.30) Vcc/r.sub.30 ≦V.sub.10 ≦(r.sub.60 +r.sub.70) Vcc/r.sub.70                 (1)

For the input terminal B,

    (r.sub.110 +r.sub.120 +r.sub.130) Vcc/r.sub.130 ≦V.sub.20 ≦(r.sub.160 +r.sub.170) Vcc/r.sub.170              (2)

In the above two equations, r₁₀ through r₁₇₀ indicate the resistancevalues of the respective resistors. Moreover, symbol "≦" means less thanor approximately equal. In equation (1) (r₁₀ +r₂₀ +r₃₀) Vcc/r₃₀represents the approximate lower limit threshold value of the inputterminal A, while (r₆₀ +r₇₀) Vcc/r₇₀ represents the approximate upperlimit threshold value of the input terminal A. In a similar manner,(r₁₁₀ +r₁₂₀ +r₁₃₀) Vcc/r₁₃₀ in equation (2) represents the approximatelower limit threshold value of the input terminal B, while (r₁₆₀ +r₁₇₀)Vcc/r₁₇₀ represents the approximate upper limit threshold value of theinput terminal B. When the input terminal A has an input level V₁₀within a range satisfying equation (1), and the input terminal B has aninput level V₂₀ within a range satisfying equation (2), the circuit ofFIG. 12 oscillates and an alternating current output signal is producedat terminal Uf. This alternating current output signal is rectified inthe rectifying circuit 203 to become a direct current output signal (ifan alternating current output signal is not generated at the terminalUf, then a direct current output signal is not produced).

The oscillation process in the circuit of FIG. 12 occurs when thevoltage levels of the input signals to the input terminals A and B bothsatisfy equations (1) and (2), with the transistors Q1 to Q7 beingswitched for example as described below.

At first with no input voltage supplied to either of the input terminalsA or B, the state of the respective transistors is; transistor Q1:OFF,transistor Q2:ON, transistor Q3:ON, transistor Q4:OFF, transistorQ5:OFF, transistor Q6:ON, and transistor Q7:ON.

Then when an input voltage which satisfies equation (1) (a voltagewithin the threshold value range having upper and lower limits expressedby equation (1)) is supplied to the input terminal A, the state of therespective transistors becomes; transistor Q1:OFF, transistor Q2:OFF,transistor Q3:OFF, transistor Q4:ON, transistor Q5:OFF, transistorQ6:ON, and transistor Q7:ON. In this case, the output conditions of thetransistors Q2, Q3, Q4, are switched and changed by the input signal ofthe input terminal A. However since an input voltage lower than thelower limit threshold value expressed by equation (2) is supplied to theinput terminal B, the output conditions of the transistors Q5, Q6, Q7and Q1 do not change. Consequently, even if a signal of a predeterminedthreshold value level is input to only one of the input terminals, thecircuit of FIG. 12 does not oscillate.

Subsequently when an input voltage satisfying equation (2) (a voltagewithin the threshold value range having upper and lower limits expressedby equation (2)) is supplied to the input terminal B, while the inputvoltage satisfying equation (1) is being input to the input terminal A,the circuit oscillates with the respective transistors being switched inthe following manner:Q6:OFF→Q7:OFF→Q1:ON→Q2:ON→Q3:ON→Q4:OFF.fwdarw.Q5:ON→Q6:ON→Q7:ON→Q1:OFF→Q2:OFF→Q3:OFF→Q4:ON→Q5:OFF→Q6:OFF→and so on.

Here the upper and lower threshold value interval (width) for the inputterminals A and B expressed by equations (1) and (2) is called a window,and the comparator illustrated by FIG. 12 having such upper and lowerthreshold values for the input level is called a window comparator.

Since the circuit of FIG. 12 oscillates only when direct current inputvoltages which respectively satisfy equations (1) and (2) are suppliedto the input terminals A and B, and can thus generate an alternatingcurrent output signal, it has the function of an AND gate. Moreover,since either of the input terminals A and B has a function of a windowcomparator, the circuit is called a two input window comparator/ANDgate. Setting the window in the window comparator, has the meaning inFIG. 12, of setting the upper and lower threshold values of the inputterminals A or B, with respect to an input level.

The circuit of FIG. 12, has the characteristic that if any one of thetransistors Q1 (i=1˜7) is faulty (for example if an short circuit faultoccurs between the base and collector of the transistor), then the phaseof the feedback loop is inverted so that a feedback oscillation cannotbe produced. Moreover, insofar as a voltage which is higher than thepower source potential Vcc, is not supplied through the respective inputterminals A and B to the collector side of the transistors Q1, Q3, Q4and transistors Q5, Q7, then switching signals cannot be output to thebases of the transistors succeeding these transistors (respectivetransistors Q2, Q4, Q5 and transistors Q6, Q1). The circuit of FIG. 12,thus has the characteristic that even with faults occurring in aplurality of the transistors (even a short circuit occurring between thebase and collector of a plurality of the transistors) then as long asinput signals (input signals satisfying equations (1) and (2)) higherthan the power source voltage are not supplied to both input terminalsA, B, it cannot oscillate. Moreover, in the case of a disconnectionfault in the resistors which determine the oscillation threshold value(the resistances which determine equation (1) and equation (2)), thecircuit of FIG. 12 has the characteristic that it cannot oscillate(similarly even if a short circuit fault occurs it cannot oscillate). Inother words, even in the worst case scenario where a short circuit ordisconnection fault occurs in the transistors and resistors which makeup the circuit, the circuit of FIG. 12 has the characteristic that;"there is no situation wherein in spite of an input voltage determinedby equations (1) and (2) being not supplied to at least both the inputterminals A and B oscillation erroneously occurs". Consequently, thecircuit of FIG. 12 is referred to as a fail-safe window comparator/ANDgate.

The rectifying circuit 203 of FIG. 12 has the function of rectifying theAC output signal produced by oscillation of the direct currentamplifying circuit 202, to give a direct current output signal. Themethod of rectifying the oscillating output signal to give a directcurrent output signal also includes amplifying the output signal of theoscillation circuit of FIG. 12 before input to the rectifying circuit.Moreover, in FIG. 12, a phase inverter amplifying circuit comprising thetransistor Q4 is inserted between but separate from the two directcurrent amplifying circuits 201, 202 as an inverter. This phase inverteramplifying circuit however may be incorporated into one of the twodirect current amplifying circuits (for example as disclosed in thebeforementioned literature such as the IEICE TRANS. ELECTRON., Vol.,E76-C, No. 3, March 1993).

FIG. 13 shows the oscillation frequency characteristics for the circuitof FIG. 12, with respect to the input voltage V12 (=V10=V20) for thecase where common inputs signals are applied to input terminals A and B,and the threshold values determined by equations (1) and (2) are set toequal values, and where; r₁₀ =r₁₁₀ =r₇₀ =16 KΩ, r₆₀ =r₁₆₀ =20 KΩ, r₃₀=r₁₃₀ =100 KΩ, r₂₀ =r₁₂₀ =6.2 KΩ, r₄₀ =r₁₄₀ =10 KΩ, r₅₀ =r₁₅₀ =1 KΩ, r₉₀=20 KΩ, r₈₀ =r₁₀₀ =r₁₈₀ =20 KΩ.

With the on-delay circuit of the present invention as described above,even if a fault occurs for example in a resistor, capacitor or the PUTmaking up the circuit, the pre-set delay time is never shortened, sothat it has extremely high fail-safe characteristics.

INDUSTRIAL APPLICABILITY

With industrial machinery requiring a high degree of safety, and whereinan on-delay circuit is used for example as a time control device, thepresent invention enables extremely high safety to be maintained, andthus has considerable industrial applicability.

We claim:
 1. An on-delay circuit comprising:a PUT oscillation circuitfor generating an oscillating pulse from a cathode terminal of a PUT(programmable uni-junction transistor) after a predetermined time periodfrom applying a signal to a signal input terminal of said PUToscillation circuit, a level conversion circuit for level converting asignal level of the oscillating pulse from the cathode terminal of saidPUT oscillation circuit and providing a level converted output, a twoinput window comparator for generating an output of logic value 1when:the signal input through the signal input terminal of said PUToscillation circuit is applied to a first input terminal of said twoinput window comparator; a rising differential signal of the levelconverted output from said level conversion circuit is applied to asecond input terminal of said two input window comparator; and signalsof a level higher than a power source potential are input to said firstand second input terminals of said two input window comparator, and aself holding circuit which feeds back a rectified output of said twoinput window comparator to said second input terminal of said two inputwindow comparator, to thereby maintain the output of said two inputwindow comparator, wherein said PUT oscillation circuit comprises:afirst resistor and a capacitor connected to each other in a first seriescircuit, said first series circuit being connected between the signalinput terminal and an ungrounded power supply line providing said powersource potential to the two input window comparator, and a secondresistor and a third resistor connected to each other in a second seriescircuit, said second series circuit being connected in parallel withsaid first series circuit including said first resistor and saidcapacitor, and wherein an anode terminal of the PUT is connected to anintermediate point between said first resistor and said capacitor, agate terminal of the PUT is connected to an intermediate point betweensaid second resistor and said third resistor, and the cathode terminalof the PUT is connected through a fourth resistor to said power supplyline, and an output is generated from an intermediate point between thecathode terminal of the PUT and the fourth resistor.
 2. An on-delaycircuit comprising:a PUT oscillation circuit for generating anoscillating pulse from a cathode terminal of a PUT (programmableuni-junction transistor) after a predetermined time period from applyinga signal to a signal input terminal of said PUT oscillation circuit, alevel conversion circuit for level converting a signal level of theoscillating pulse from the cathode terminal of said PUT oscillationcircuit and providing a level converted output, a two input windowcomparator for generating an output of logic value 1 when:the signalinput through the signal input terminal of said PUT oscillation circuitis applied to a first input terminal of said two input windowcomparator; a rising differential signal of the level converted outputfrom said level conversion circuit is applied to a second input terminalof said two input window comparator; and signals of a level higher thana power source potential are input to said first and second inputterminals of said two input window comparator, and a self holdingcircuit which feeds back a rectified output of said two input windowcomparator to said second input terminal of said two input windowcomparator, to thereby maintain the output of said two input windowcomparator, wherein said level conversion circuit has a fifth resistorand a sixth resistor for dividing a voltage of said oscillating pulsefrom the PUT oscillation circuit, and incorporates a PNP transistor,said PNP transistor having an emitter connected to a power supply lineproviding said power source potential of the two input windowcomparator, a collector connected through a seventh resistor to earth,and a base connected to an intermediate point between the fifth resistorand the sixth resistor, and said level converted output representing asignal generated at an intermediate point between the collector and theseventh resistor.
 3. An on-delay circuit comprising:a PUT oscillationcircuit for generating an oscillating pulse from a cathode terminal of aPUT (programmable uni-junction transistor) after a predetermined timeperiod from applying a signal to a signal input terminal of said PUToscillation circuit, a level conversion circuit for level converting asignal level of the oscillating pulse from the cathode terminal of saidPUT oscillation circuit and providing a level converted output, a twoinput window comparator for generating an output of logic value 1when:the signal input through the signal input terminal of said PUToscillation circuit is applied to a first input terminal of said twoinput window comparator; a rising differential signal of the levelconverted output from said level conversion circuit is applied to asecond input terminal of said two input window comparator; and signalsof a level higher than a power source potential are input to said firstand second input terminals of said two input window comparator, and aself holding circuit which feeds back a rectified output of said twoinput window comparator to said second input terminal, to therebymaintain the output of said two input window comparator, wherein:aresistor and a four terminal capacitor are connected to the first inputterminal of the two input window comparator which receives the signalinput through the signal input terminal of said PUT oscillation circuitone end of the resistor being connected to the signal input terminal ofthe PUT oscillation circuit; said four terminal capacitor having twoterminals of one electrode plate connected to another end of theresistor and to the first input terminal of the window comparator, saidfour terminal capacitor having two terminals of a second electrode plateconnected between a power supply line providing the power sourcepotential and the window comparator, and wherein predetermined thresholdvalue ranges are set which define an upper limit value and a lower limitvalue for input signal levels for the two input terminals of the twoinput window comparator.
 4. An on-delay circuit comprising:a PUToscillation circuit for generating an oscillating pulse from a cathodeterminal of a PUT (programmable uni-junction transistor) after apredetermined time period from applying a signal to a signal inputterminal of said PUT oscillation circuit, a level conversion circuit forlevel converting a signal level of the oscillating pulse from thecathode terminal of said PUT oscillation circuit and providing a levelconverted output, a two input window comparator for generating an outputof logic value 1 when:the signal input through the signal input terminalof said PUT oscillation circuit is applied to a first input terminal ofsaid two input window comparator; a rising differential signal of thelevel converted output from said level conversion circuit is applied toa second input terminal of said two input window comparator; and signalsof a level higher than a power source potential are input to said firstand second input terminals of said two input window comparator, whereinsaid power source potential is drawn from an ungrounded power supplyline, said level conversion circuit comprising a switching device havinga pair of main terminals and a control terminal, said main terminalsrespectively connected to said power source potential and to a powersource return terminal, and said control terminal connected to receivethe oscillating pulse from the cathode terminal of said PUT oscillationcircuit; and a self holding circuit which feeds back a rectified outputof said two input window comparator to said second input terminal ofsaid two input window comparator, to thereby maintain the output of thewindow comparator.
 5. An on-delay circuit according to claim 1, whereinsaid level conversion circuit is connected for reducing the signal levelof the oscillating pulse from a level higher than the power sourcepotential to a level within a range between the power source potentialand ground.